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From: crew@pitt.UUCP (Al Crew)
Newsgroups: comp.os.minix
Subject: Re: Query about level-triggered interrupts on the PS/2
Message-ID: <4464@pitt.UUCP>
Date: 18 Jan 89 04:20:53 GMT
References: <1910@ast.cs.vu.nl> <3187@ima.ima.isc.com>
Reply-To: crew@vax.cs.pittsburgh.edu.UUCP (Al Crew)
Organization: Univ. of Pittsburgh Computer Science
Lines: 6

Yes, I/O devices often spec a "recovery time" between successive accesses
to controller chips.  (I know this to be true of most of Intel's
controllers - 8255/8253/8254/etc).  In most cases it is on the
order of 1 microsecond.  Successive I/O operations to an I/O
controller can violate this spec.  The wait states inserted
by the old pc bus may have "masked" a problem.