Path: utzoo!utgpu!attcan!uunet!lll-winken!ames!ncar!tank!uwvax!astroatc!nicmad!madnix!aaron
From: aaron@madnix.UUCP (Aaron Avery)
Newsgroups: comp.sys.amiga
Subject: Re: Multiple Serial Ports (Re: vt100 v2.9)
Message-ID: <399@madnix.UUCP>
Date: 15 Jan 89 14:01:10 GMT
References: <8812150227.AA09671@postgres.Berkeley.EDU> <14049@oberon.USC.EDU> <554@sunkisd.CS.Concordia.CA> <3241@sugar.uu.net> <147@ziggy.UUCP> <373@madnix.UUCP> <150@ziggy.UUCP> <385@madnix.UUCP> <154@ziggy.UUCP> <393@madnix.UUCP>
Reply-To: aaron@madnix.UUCP (Aaron Avery)
Organization: ASDG Incorporated
Lines: 20

In article <393@madnix.UUCP> aaron@madnix.UUCP (Aaron Avery) writes:
>The Z8530 has DMA block transfer support built in. For single byte reads
>(perhaps the norm), you set the block length to 1, and the byte will be
>stuffed into main memory and you will get an interrupt from the SCC. When

I wanted to add a bit to that last message -- sorry.

This implementation will have terrific throughput for protocol-based transfers,
but will have more host CPU overhead than an on-board processor approach for
normal, single byte per request, communications. This can be overcome quite
easily by adding FIFO buffers to the board, and a bit more DMA control logic.
This brings the cost up closer to the on-board processor design, but should
be both easier on the main processor (now that reads are buffered on-board),
and have greater throughput.

-- 
Aaron Avery, ASDG Inc.         "A mime is a terrible thing to waste."
                                                             -- Robin Williams
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