Path: utzoo!utgpu!attcan!uunet!lll-winken!ames!ucsd!ncr-sd!greg
From: greg@ncr-sd.SanDiego.NCR.COM (Greg Noel)
Newsgroups: comp.sys.amiga
Subject: Re: Multiple Serial Ports (Re: vt100 v2.9)
Message-ID: <699@ncr-sd.SanDiego.NCR.COM>
Date: 16 Jan 89 04:11:48 GMT
References: <154@ziggy.UUCP> <393@madnix.UUCP> <399@madnix.UUCP>
Organization: NCR Corporation, Rancho Bernardo
Lines: 12

In article <399@madnix.UUCP> aaron@madnix.UUCP (Aaron Avery) writes:
>.... This can be overcome quite
>easily by adding FIFO buffers to the board, and a bit more DMA control logic.
>This brings the cost up closer to the on-board processor design, but should
>be both easier on the main processor ..., and have greater throughput.

It's interesting that this discussion is recreating the design of the DH-11,
an I/O controller used on the PDP-11 (and later on the VAX series).  It was
moderately tricky to program, but could easily sustain a data rate that the
"replacement" DZ-11 could only dream about.
-- 
-- Greg Noel, NCR Rancho Bernardo   Greg.Noel@SanDiego.NCR.COM  or  greg@ncr-sd