Path: utzoo!attcan!uunet!lll-winken!ncis.llnl.gov!helios.ee.lbl.gov!nosc!ucsd!rutgers!mailrus!sharkey!cfctech!teemc!mibte!jbh From: jbh@mibte.UUCP (James Harvey) Newsgroups: comp.sys.cbm Subject: Re: Another info request for old CBM computers Summary: FOUND it Message-ID: <2749@mibte.UUCP> Date: 22 Jan 89 01:58:12 GMT References: <2035@iitmax.IIT.EDU> <448@csd4.milw.wisc.edu> <2748@mibte.UUCP> <502@csd4.milw.wisc.edu> Organization: Michigan Bell Telephone Company Lines: 142 In article <502@csd4.milw.wisc.edu>, jgreco@csd4.milw.wisc.edu (Joe Greco) writes: > In article <5745@cbmvax.UUCP> fred@cbmvax.UUCP (Fred Bowen) writes: >>The SuperPET bank switching is done through a register located at $EFFC, >>into which you place the bank number (0-15). There are 16 4K RAM banks which >>which appear in memory at $9000-$9FFF. There are other RAM and ROM expansion >>cartridges which appear at $A000. > > The original question was re: 8096, not re: SuperPET....! > : Well, I found the book on the PET 64K memory expansion. This is Part Number 324008, I assume it is the same board as in an official 8096 (Was there an official 8096?). I quote (with apologys to CBM): Expansion memory can be mapped into main memory addresses $8000 through $FFFF. Only 2 of the 16K expansion blocks can reside in main memory at one time. This provides an additional 32 K bytes of memory to the user. Selection of the expansion blocks is by bits 2 and 3 of the expansion memory control register. Each 16K block has a 16K alternate that can be selected by bits 2 and 3 of the control register. Main memory addresses $8000 through $BFFF can only be mapped by expansion blocks 0 or 1. Main memory addresses $C000 through $FFFF can only be mapped by expansion blocks 2 or 3. < there is a drawing showing four 16K blocks of expansion memory, zero and one pointing to addresses $8000 to $BFFF, two and three pointing to $C000 to $FFFF. > Control of the expansion memory is through a memory control register on the Expansion Memory Board located at $FFF0. The memory control register provides selection of 16K blocks, write protection, enabling the expansion memory, I/O peek through and Screen peek through. Because the memory control register is write only, a copy should be kept in the lower 32k of main memory. < there is a drawing depicting the memory control register Bit does ------- ----- 0 Write Protect $8000 - $BFFF on expansion board (if 1) 1 Write Protect $C000 - $FFFF on expansion board (if 1) 2 block select (see table below) 3 block select (see table below) 4 Reserved 5 Screen Peek Through $8000 - $8FFF (if 1) 6 I/O Peek Through $E800 - $EFFF (if 1) 7 Enable (if 1, power up defaults to zero) The block map is drawn as follows Bits 2 and 3 Blocks ------------- ------ 0,0 2 and 0 0,1 2 and 1 1,0 3 and 0 1,1 3 and 1 I/O handling I/O in the 8032 consists of the following five devices 1. a 6520 PIA at $E810 2. a 6520 PIA at $E820 3. a 6522 PIA at $E840 4. a CRT controller at $E880 5. Screen memory at $8000 through $87FF j These may be accessed in two ways. First is to simply switch out the expansion memory and restore main memory. This may be already accomplished by the memory manager software when a CBM I/O routine is called. Second way (necessary when a RAM loaded application program accesses I/O) uses the I/O peek through feature. Bit 6 of the control register enables I/O peek through. Accessing screen memory is accomplished in the same way as accessing the other IO devices. When accessed, screen memory is seen as 25 lines of 80 columns. The data is stored row-wise as sequential bytes. The CRT circuitry cannot display out of the expansion ram. A suggested memory manager function is to page whole screen fulls of data out of the expansion ram. Interrupt Processing The 6502 micro processor is designed for a simple system architecture in which the lower 32 K of the address space is RAM and the upper 32K is ROM. This allows the microprocessor to fetch the starting address of the first instruction out of ROM upon reset. The result is that three hardware vectors are stored in addresses $FFFA - $FFFF. The memory manager must accomplish the following functions. 1. Ensure that there is a valid address at each ROM address in the two 16K expansion blocks that are active. The only exception is if interrupts are disabled by a SEI instruction executed before bit 7 is set to a 1. 2. To avoid being interrupted when changing a vector execute a SEI. 3. The ROM interrupt vectors in the CBM point to routines in ROM which are not accessible when the expansion memory is selected. For that reason, the memory manager should a) set the vectors to point at at a routine that switches to main memory mode, b) call the interrupt service routine, and c) restore the expansion memory mode. End of quotes. > >>speed serial line. A standard RS232 connector is included. I don't know of >>any IEEE-RS232 interfaces, but I do know IEEE-Centronics interfaces are still >>available. > > Um, Fred, where? > If you are REALLY desparate, I think Black Box has one for $200-$300. > -- > jgreco@csd4.milw.wisc.edu Joe Greco at FidoNet 1:154/200 > USnail: 9905 W Montana Ave PunterNet Node 30 or 31 > West Allis, WI 53227-3329 "These aren't anybody's opinions." > Voice: 414/321-6184 Data: 414/321-9287 (Happy Hacker's BBS) -- Jim Harvey | "Ask not for whom the bell Michigan Bell Telephone | tolls and you will only pay 29777 Telegraph | Station-to-Station rates." Southfield, Mich. 48034 | ulysses!gamma!mibte!jbh