Path: utzoo!attcan!uunet!husc6!bloom-beacon!mit-eddie!uw-beaver!microsoft!w-colinp From: w-colinp@microsoft.UUCP (Colin Plumb) Newsgroups: comp.arch Subject: Re: Rx000 byteorder Message-ID: <331@microsoft.UUCP> Date: 23 Jan 89 08:50:31 GMT References: <76@melba.oz> Reply-To: w-colinp@microsoft.uucp (Colin Plumb) Organization: very little Lines: 17 zs01+@andrew.cmu.edu (Zalman Stern) wrote: > If I rember correctly, the AMD 29000 > looks at its byte order pin at reset time and the setting thereof only > affects load/store operations. I assume this is implemented with some sort > of switchable permutation circuit on the D bus... The 29000 has a bit in the configuration register. This isn't intended to be set more than once between resets, but I don't see anything stopping you from making it per-process context. Also, the 29000 has insert/extract byte and halfword instructions; it's these the byte sex bit modifies. Basically, it involves xoring the low two bits if the address with 11 (bytes) or 10 (words) if the sex isn't what's expected. If your machine silently ignores unaligned addresses, xor with 11 all the time. -- -Colin (uunet!microsof!w-colinp)