Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!amdahl!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: Intel's N-10: 150 MIPS?
Message-ID: <14044@cup.portal.com>
Date: 28 Jan 89 19:07:56 GMT
References: <3300047@m.cs.uiuc.edu>
Organization: The Portal System (TM)
Lines: 20

>There's a blurb in the Jan. 30 issue of *Buisness Week* about 
>Intel disclosing a 150 MIP processor at the Feb. ISSCC.
>The code name for the project is the N-10, and it alledgedly
>is intended as a coprocessor for the 486.  Anyone have the scoop
>on this?  Is it hardware, vaporware, hypeware, or just rumorware?

It's SCAREWARE :-).  It's a challenge to everybody else in the biz.

More than a co-processor, I hear.  Two modes:  integer only
and integer/floating point.  Integer only:  Good ol' RISC.  Integer/
floating point:  one integer and one floating point instruction per
cycle.  At 50 MHz, that's 100 "MIPS".  Since the floating-point can
be multiply/accumulate, that's 150 "MOPS".  Two 4K, on-chip caches.
TLBs.  Should be a nice, if expensive, chip.  Can't wait for ISSCC!

Love sentence fragments.
 
>University of Illinois at Urbana-Champaign

Go Illini!