Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!pasteur!ucbvax!decwrl!sun!pitstop!sundc!seismo!uunet!mcvax!enea!kth!draken!tut!jja From: jja@etana.tut.fi (Ahola Jari) Newsgroups: comp.arch Subject: Re: Cache models and program behavior Message-ID: <5941@etana.tut.fi> Date: 30 Jan 89 10:34:10 GMT References: <4122@pt.cs.cmu.edu> Sender: News@tut.fi Lines: 20 From article <4122@pt.cs.cmu.edu>, by dkirk@k.gp.cs.cmu.edu (Dave Kirk): > I am looking for references to techniques for modelling memory access > patterns and approximate cache hit (miss) rates. I'd like to reduce > specific access strings to a few parameters which could be used to > determine approximate cache hit (miss) rates. > > Additional references have been hard to come by, and would be greatly > appreciated. > Best reference to my knowledge is Pohm & Agrawahl: High speed memory systems which covers many cache organisations and models for modelling their performance. -jja Jari 'jja' Ahola |Tampere University of Technology, Software Systems Lab Opiskelijankatu 16A12 |P.O. Box 527, 33101 Tampere, Finland 33720 Tampere, Finland|Tel (intl) 358 31 162708 (work)/358 31 174009 (home) Puh. 931-174009 |Net address: jja@tut (UUCP) AHOLA@FINTUTA (BITNET)