Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!rutgers!apple!amdcad!sun!pitstop!sundc!seismo!uunet!pdn!alan From: alan@pdn.nm.paradyne.com (Alan Lovejoy) Newsgroups: comp.arch Subject: Re: When is RISC not RISC? Message-ID: <5494@pdn.nm.paradyne.com> Date: 1 Feb 89 17:25:12 GMT References: <170@microsoft.UUCP> <4008@hubcap.UUCP> <747@atanasoff.cs.iastate.edu> <10030@diamond.csl.sony.JUNET> Reply-To: alan@pdn.nm.paradyne.com (0000-Alan Lovejoy) Organization: Paradyne Corporation, Largo, Florida Lines: 35 In article <10030@diamond.csl.sony.JUNET> diamond@csl.sony.JUNET (Norman Diamond) writes: >In article <747@atanasoff.cs.iastate.edu>, hascall@atanasoff.cs.iastate.edu (John Hascall) writes: >> > Sigh, RISC doesn't mean a small number of instructions. RISC means.... >Maybe reduced number of KINDS of instructions. > >Having an add instruction for a little-endian word and another for a >big-endian word strikes me as a little silly (maybe a big silly :-), >but still riscy. RISC should stand for "Reduced Instruction Set Complexity". This means minimizing the number of different instruction formats, having only one instruction size (e.g., 32 bits), eliminating instructions that can't be performed in once cycle with a reasonable amount of hardware or without making the cycle-time considerably longer that is needed for most instructions, and a host of other things less well characterized by the nominal semantics of R.I.S.C. (caches, pipelines, parallelism...). Whether an architecture is little-endian or big-endian depends upon how it maps byte adressess (well, on a byte-addressed machine, anyway) of the bytes in a word or longword to the arithmetic significance of those bytes. Once a word or longword has been fetched from memory into a register, the bytes of that word or longword no longer have addresses, so the endianness becomes undefined. Since traditional RISC architectures only allow load and store operations to reference memory, all other operations must be carried out on values in registers. So there would be no need to have big-endian and little-endian versions of "ADD" or any other operation besides LOAD and STORE. -- Alan Lovejoy; alan@pdn; 813-530-2211; ATT-Paradyne: 8550 Ulmerton, Largo, FL. Disclaimer: I do not speak for ATT-Paradyne. They do not speak for me. ___________ This Month's Slogan: Reach out and BUY someone (tm). ___________ Motto: If nanomachines will be able to reconstruct you, YOU AREN'T DEAD YET.