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From: rodman@mfci.UUCP (Paul Rodman)
Newsgroups: comp.arch,comp.misc,comp.lang.misc,comp.protocols.misc
Subject: Re: When is RISC not RISC?
Message-ID: <635@m3.mfci.UUCP>
Date: 31 Jan 89 16:04:31 GMT
References: <170@microsoft.UUCP> <4008@hubcap.UUCP> <747@atanasoff.cs.iastate.edu>
Sender: rodman@mfci.UUCP
Reply-To: rodman@mfci.UUCP (Paul Rodman)
Organization: Multiflow Computer Inc., Branford Ct. 06405
Lines: 40

In article <747@atanasoff.cs.iastate.edu> hascall@atanasoff.cs.iastate.edu (John Hascall) writes:
>
>  In response to someone proposing adding instructions to a RISC
>  machine, I wrote:
> 
>>>  Here it is again, adding instructions to a RISC machine... won't
>>>  be long before we have a RISC machine with more instructions
>>>  than a VAX.... :-)
>
>  And was "corrected" by someone* thusly:
>   
>> And again...
>> Sigh, RISC doesn't mean a small number of instructions.  RISC means....
>
>   REDUCED Instruction Set Computer (i.e., a reduced number of instructions)


  At the risk of starting more pointless RISC/CISC flameage, let me add
my 2 cents worth here: (I know many of you out there won't agree....:-) 

The term RISC has been terribly misused, but my personal definition has
be widened to include machines that don't have a "small" number of 
instructions. 

E.g. the Multiflow Trace,( which I am using to compose this mail) has 
a VERY large space of possible instructions. I would still term this
machine RISCy  as each functional unit is controlled directly 
by the instruction word, and is decoupled from instruction packets that
are wired to other functional units. Hence the original purpose of the
RISC idea is served.

Conventional RISCs are designed to approach 1 "op" per cycle. We designed
a multiple-functional unit machine that executes >1 ops / cycle.
The VLIW compiler is considerably "smarter" than a typical
RISC compiler, and the compiler <-> hardware fusion is even more important
than for a simple RISC, but the basic mind set is still the same.


    Paul K. Rodman
    rodman@mfci.uucp