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From: davidsen@steinmetz.ge.com (William E. Davidsen Jr)
Newsgroups: comp.arch,comp.misc,comp.lang.misc,comp.protocols.misc
Subject: Re: Unification of big and little endian architectures.
Keywords: dump little-endian strings
Message-ID: <13063@steinmetz.ge.com>
Date: 1 Feb 89 17:06:17 GMT
References: <170@microsoft.UUCP> <4008@hubcap.UUCP> <482@babbage.acc.virginia.edu> <7193@csli.STANFORD.EDU> <1371@X.UUCP> <5462@pdn.nm.paradyne.com> <86957@sun.uucp>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: General Electric CRD, Schenectady, NY
Lines: 28

In article <86957@sun.uucp> khb@sun.UUCP (Keith Bierman - Sun Tactical Engineering) writes:

| Perhaps I am missing something...but it appears to me that this
| increases the size of the instruction set (and therefore gate size),
| so we will have a more complex machine, less space for registers/other
| goodies, and what we gain seems to be rather a small win.... 

  This is really not in keeping with (my) concept of RISC. Rather than
many new instructions, one instruction with an argument would allow
setting the endedness of the load/store operations.

	SEL		; Set endian little
	MOV	R14,XX	; Start compare...

  Please note: I am not saying that this is a good thing to do, just
that it would seem easier to have one instruct control the endedness.
Sure makes a neat way to flip the bits in a word, ie:

	SEL		; little endian
	MOV	R14,XX	; Load xx into R14
	SEB		; big endian
	MOV	XX,R14	; store, reversed bits

  Hummm... maybe this is a good idea, after all.
-- 
	bill davidsen		(wedu@ge-crd.arpa)
  {uunet | philabs}!steinmetz!crdos1!davidsen
"Stupidity, like virtue, is its own reward" -me