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From: hascall@atanasoff.cs.iastate.edu (John Hascall)
Newsgroups: comp.arch,comp.misc,comp.lang.misc,comp.protocols.misc
Subject: Re: Unification of big and little endian architectures.
Summary: Coming full circle
Message-ID: <731@atanasoff.cs.iastate.edu>
Date: 26 Jan 89 15:34:12 GMT
References: <170@microsoft.UUCP> <4008@hubcap.UUCP> <482@babbage.acc.virginia.edu> <7193@csli.STANFORD.EDU> <1371@X.UUCP> <5462@pdn.nm.paradyne.com>
Reply-To: hascall@atanasoff.cs.iastate.edu (John Hascall)
Organization: Iowa State U. Computer Science Department, Ames, IA
Lines: 32

(0000-Alan Lovejoy) writes:
 
 
>It seems that several of the ccurrent RISC architectures provide for 
>either big or little endian operation (Rx000, 88k, 29k, ?).  They do
>this buy providing a global operating status that can be set by the
>user to either big or little endian.
 
>It would be better to provide load and store operations that are
>specifically big or little endian:
 
>LLE.W -- load little endian word
>SLE.W -- store little endian word
>LLE.L -- load little endian long
>SLE.L -- store little endian long
>LBE.W -- load big endian word
>SBE.W -- store big endian word
>LBE.L -- load big endian long
>SBE.L -- store big endian long
 
  [...example of using such a feature omitted...]

  Here it is again, adding instructions to a RISC machine... won't
  be long before we have a RISC machine with more instructions
  than a VAX.... :-)
 

 John Hascall
 ISU Comp Center
 Ames, IA