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From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch,comp.misc,comp.lang.misc,comp.protocols.misc
Subject: Re: Unification of big and little endian architectures.
Message-ID: <14005@cup.portal.com>
Date: 27 Jan 89 18:48:34 GMT
References: <170@microsoft.UUCP> <4008@hubcap.UUCP> <482@babbage.acc.virginia.edu> <7193@csli.STANFORD.EDU> <1371@X.UUCP> <5462@pdn.nm.paradyne.com> <731@atanasoff.cs.iastate.edu>
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>  Here it is again, adding instructions to a RISC machine... won't
>  be long before we have a RISC machine with more instructions
>  than a VAX.... :-)

And again...

Sigh, RISC doesn't mean a small number of instructions.  RISC means
simple instructions that, for one thing, all fit in the same uniform
pipeline.  The number of instructions is a factor, there's no reason
to have more than are really necessary, but if the instructions are
of the right nature, simple to decode and uniform in semantics, you
can have a gazillion of them.  Thus, the emphasis is on instruction
*encodings* and *semantics*, NOT THE QUANTITY.

So, adding the loads and stores in both little and big endian varieties
is not necessarily an anit-RISC idea.  In fact, since they add to the
richness of the instruction set with out requiring new hardware (the
little/big endian hardware is already there in some machines!), they
are very good candidates for new instructions.  What about encoding?
One extra bit will do, and this is not hard to decode, it should not
increase decode time.

What about use?  Yes the code generators can be trained to deal with
this.  But what about passing pointers to the operating system?  I
guess we would need two versions of many (most?) system calls....
What else?

If, considering all the software implications (which I have not had
time to do), this works, I wish we had implemented it in the 29K.