Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!haven!rutgers!att!pegasus!ech
From: ech@pegasus.ATT.COM (Edward C Horvath)
Newsgroups: comp.sys.m68k
Subject: Re: MC68030 Burst Mode performances (was "68030 MMU overhead query")
Message-ID: <2529@pegasus.ATT.COM>
Date: 19 Jan 89 17:22:10 GMT
References: <906@cernvax.UUCP>
Organization: AT&T ISL Middletown NJ USA
Lines: 39

From article <906@cernvax.UUCP>, by rbt@cernvax.UUCP (rbt):
! We are now working on a new board with such a processor and fast RAMs.
! The problems is that our RAM chips are fast for us but not for the
! processor (we are using 100 ns static RAM memory). The burst mode gives
! us a 2-2-2-2 cycle, where the processor must wait 1 cycle before
! receiving the next longword. The tests we made on ASSEMBLER programs,
! with data and instruction caches enabled, gave a degradation of the
! system performances. I expect a FORTRAN or PASCAL program to run slower
! with burst mode enabled. Only when the board will be upgraded to fast
! (45 ns) static RAMS or fast Nibble-Mode dynamic memories we will
! expect an improvement, with a real 2-1-1-1 sequence. Again, only on
! compiled code. ASSEMBLER programs are usually peculiar: they do not
! process big bunches of data and their stream is not very linear.
!  
! In conclusion, burst mode is useful when:
!    o the RAM is fast enough to follow the processor 2-1-1-1 sequence;
!    o data and code move in regions.
!  
! For the first point the answer is: buy RAM as fast as required by the
! processor: this is expensive but can be done for the MC68030. The
! problem will become more serious when the MC68040 will be available. I
! heard Motorola saying (unofficially) that the speed improvements for
! this processor cannot go very further since the external devices will
! not be able to run at the required speed.

It seems to me that there's an alternative: build the memories WIDER
rather than FASTER.  Given that the processor is going to pull a longword
per cycle in straight-line code, store alternating longwords in two 2-cycle
RAMs which are operating out of phase.

Notice that we're always using "read ahead," so a branch to the bank that's
in mid-memory-cycle will cost one wait state while that bank completes its
(useless) fetch (...-1-3-1 v. optimal ...-1-2-1).  A branch to the bank
that just finished takes 2 cycles for the RAM as well as the processor.

Could be a damned sight cheaper than 45ns parts if you can hack the
increased chipcount.

=Ned Horvath=