Path: utzoo!attcan!uunet!tektronix!tekig5!brianr
From: brianr@tekig5.PEN.TEK.COM (Brian Rhodefer)
Newsgroups: sci.electronics
Subject: Re: Looking for isolated DAC chip
Summary: Try blasting your TRIACS directly
Message-ID: <3684@tekig5.PEN.TEK.COM>
Date: 16 Jan 89 19:34:13 GMT
References: <1378@ucsd.EDU>
Reply-To: brianr@tekig5.PEN.TEK.COM (Brian Rhodefer)
Organization: Tektronix, Inc., Beaverton,  OR.
Lines: 76

A friend and I have dabbled with the construction of
stage lighting control systems for many years now,
with emphasis on computer-controlled lighting system.

Our current approach is to control a network of power
modules from a 'human interface' program running on an
Amiga computer.  Each module drives up to eight loads
at independently settable power levels, with 7-bit
resolution. This sounds fairly close to your application.

Each channel of one of our power modules is driven by
a TRIAC, whose gate-trigger signal is optically coupled
to one bit of (surprise!) an eight-bit latch.  In our
case, this "latch" is an 8-bit output port of a module's
embedded microcontroller, but you may be able to use the
TTL latch you've mentioned.

Control of the power delivered to each load is achieved by
varying the delay, relative to the power line zero-crossing,
of the pulses generated on the associated latch bit.

At 60 Hz, each powerline halfcycle is 8333 microseconds in duration.
Splitting this period up into 128 levels (for 7-bit control) gives
a timing resolution requirement of very nearly 65 microseconds.

The desired power levels of all the channels are sorted in
order of decreasing output, and are then translated into a list
of "firing data".  Each firing datum consists of two pieces of
information:  the pattern of bits to send to the latch, and the
amount of time that must elapse before the next firing datum is used.

Firing-list scanning begins at the zero-crossing of the power line.
The first datum specifies a null firing pattern (all channels OFF),
and gives the delay from zero crossing until the the highest-output
channel(s) must fire.  The delay is loaded into a countdown timer,
which ticks down once per 65us (well, we use 64us...).  Expiration
of the timer causes an interrupt, whose service routine pulls the
next firing datum off the list, stuffs the firing pattern into the
latch, and re-loads the timer with the precomputed relative delay.


The hardware requirements for this approach, beyond the TTL latch
you mentioned, and its assumed controlling processor, are these:

1) A zero-crossing detector connected to the controlling processor.
   We use a bridge to full-wave rectify the mains voltage; the 120Hz
   signal, through a suitable power-resistor divider, holds a
   2N3904-ish transistor ON for all line voltages in excess of 10
   volts or so.  When the transistor cuts OFF, another transistor
   is allowed to extract stored energy from a capacitor and energize
   the transmitting LED of a 4N26-ish optocoupler, whose isolated
   output is used to interrupt our controlling processor.


2) One optocoupler per channel of output drive.  We use optocouplers
   whose receivers are themselves TRIACS, albeit low-power ones.
   When these come ON, they complete a path from Main Terminal 2
   of the power TRIAC, through a 100 ohm limiting resistor, to the
   gate of the power TRIAC.  This gives ampere-magnitude firing
   pulses to the power devices, which get them turned on quite
   nicely.

3) Transient suppression circuitry for each power channel.   The
   recommended practice  is to use power inductors, in the 100 to
   500 microhenry range, to retard the rate-of-rise of the load
   current.  In the past, these were necessary to prevent hot-spots
   from forming in the power TRIAC during turn-on.  Today's devices
   are more rugged, and turn on faster, but you'll probably find that
   unless you tame the spikes down a bit, you'll get crosstalk among
   your channels that'll have them triggering each other.


Hoping to be Helpful,


Brian Rhodefer   ...!tektronix!tekig5!brianr