Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!uxc!uxc.cso.uiuc.edu!mcdurb!aglew From: aglew@mcdurb.Urbana.Gould.COM Newsgroups: comp.arch Subject: Fujitsu SPARC Interlocks Message-ID: <28200269@mcdurb> Date: 6 Feb 89 03:39:00 GMT Lines: 54 Nf-ID: #N:mcdurb:28200269:000:2071 Nf-From: mcdurb.Urbana.Gould.COM!aglew Feb 5 21:39:00 1989 I thought this was worth noting in this newsgroup: From Electronic Design, Dec 8, 1988 (paraphrased, without permission): Fujitsu is implementing a SPARC chip with Harvard architecture, split I and D buses, 64 bits wide bus (1 or 2? I dunno) --> Pipeline interlocks in the chip's circuits eliminate timing --> problems that might result when software written for earlier --> Sparc CPUs is running. --- In case you haven't guessed, one of my pet peeves is people who say that interlocks are no longer necessary because the compiler will handle them. Until the advent of binary compilers for ABIs, interlocks will be necessary. No two implementations of the same device will have the same timings. So, the question becomes: WHAT interlocks are appropriate? Delayed branches are a fairly common type of interlock avoidance technique - but does the need to interlock on the second delay slot, in the latest MIPS machines, cost any more than the lack of need of an interlock in the first? (I suppose that the timing is relaxed, but what about complexity). Machine designers: which interlocks are the most complex, the most likely to be timing critical? Compiler writers: which are the hardest interlocks to optimize around? Performance Analysts: which interlocks are exercised most frequently? What do they cost? (the MIPS pixie data has been useful here) Technology prophets: what ways is the technology likely to go? Longer or shorter branch delays? Memory latencies? --- You don't want to paint yourself into a corner by not having interlocks, then to find that this increases the complexity of a multiple issue implementation of your architecture. Andy "Krazy" Glew aglew@urbana.mcd.mot.com uunet!uiucdcs!mcdurb!aglew Motorola Microcomputer Division, Champaign-Urbana Design Center 1101 E. University, Urbana, Illinois 61801, USA. My opinions are my own, and are not the opinions of my employer, or any other organisation. I indicate my company only so that the reader may account for any possible bias I may have towards our products.