Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!gatech!udel!rochester!pt.cs.cmu.edu!andrew.cmu.edu!jk3k+ From: jk3k+@andrew.cmu.edu (Joe Keane) Newsgroups: comp.arch Subject: Re: When is RISC not RISC? Message-ID: Date: 7 Feb 89 21:54:37 GMT References: <4592@tekgvs.LABS.TEK.COM> Organization: Mathematics, Carnegie Mellon, Pittsburgh, PA Lines: 8 In-Reply-To: <4592@tekgvs.LABS.TEK.COM> Keith Ericson writes: > Seems to me that the "reduced" is a totally incorrect moiniker (sp?): the > truly salient point is that all the instructions are equal length, to reduce > problems maintaining the instruction pipeline. As much as i dislike VAX instruction encoding, i can't agree with this. Single-size instructions are nice, but you'll pay a price in code density. The RT has two instruction sizes, and i think it was the right choice.