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Path: utzoo!utgpu!dennis
From: dennis@gpu.utcs.toronto.edu (Dennis Ferguson)
Date: Tue, 7-Feb-89 22:21:13 EST
Message-ID: <1989Feb7.222113.7622@gpu.utcs.toronto.edu>
Organization: University of Toronto Computing Services
Newsgroups: comp.arch
Subject: Re: When is RISC not RISC?
References: <4592@tekgvs.LABS.TEK.COM> <cXvqKRy00Wo=0TV282@andrew.cmu.edu>
Reply-To: dennis@gpu.utcs.toronto.edu (Dennis Ferguson)

In article <cXvqKRy00Wo=0TV282@andrew.cmu.edu> jk3k+@andrew.cmu.edu (Joe Keane) writes:

>Single-size instructions are nice, but you'll pay a price in code density.  The
>RT has two instruction sizes, and i think it was the right choice.

Except that, because they had to encode both the OP code and a couple
of registers into 16 bit instructions, the RT ended up with only 16
registers.  There just isn't enough room for more registers if you have
to accomodate the entire instruction set in 16 bits.

Personally, I think that was the wrong choice.  I'd think I'd rather
have longer instructions and more registers, thanks.

Dennis Ferguson
University of Toronto