Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!sharkey!atanasoff!hascall
From: hascall@atanasoff.cs.iastate.edu (John Hascall)
Newsgroups: comp.arch
Subject: Re: Endian reversing MOVEs
Keywords: Code-wars
Message-ID: <776@atanasoff.cs.iastate.edu>
Date: 8 Feb 89 15:14:20 GMT
References: <759@atanasoff.cs.iastate.edu> <MXvZBhy00W428s8WI0@andrew.cmu.edu> <772@atanasoff.cs.iastate.edu> <QXvqHvy00Vs887oooq@andrew.cmu.edu>
Reply-To: hascall@atanasoff.cs.iastate.edu (John Hascall)
Organization: Iowa State U. Computer Science Department, Ames, IA
Lines: 49

In article <QXvqHvy00Vs887oooq@andrew.cmu.edu> zs01+@andrew.cmu.edu (Zalman Stern) writes:
>> *Excerpts from ext.nn.comp.arch: 7-Feb-89 Re: Endian reversing MOVEs Joe*
>> *Keane@andrew.cmu.edu (713)*
>> That's 11 memory references for something which has nothing to do with memory.
>> It only takes 6 instructions (0 memory references) on the RT.

>The RT has two advantages here. First, has no addressing modes to worry about.
>Second, the RT has instructions for moving characters around within registers.
>The first is a result of a RISC load/store architecture. The second might not
>exactly be RISC, but probably isn't too far off. (I don't have any figures as to
>how often the MC03 type instructions are used but they shouldn't add much
>complexity.)

>       ... These all assume you are byte switching a value from one register
>into a distinct register. This is a minor difference from the original macro,
>but I think it is the reasonable case to consider.

>Here's the RT code:

>mc31    SRC, DEST       ; DEST[3] = SRC[1]
>mc23    DEST, DEST      ; DEST[2] = DEST[3]
>mc32    SRC, DEST       ; DEST[3] = SRC[2]
>mc13    DEST, DEST      ; DEST[1] = SRC[3]
>mc30    SRC, DEST       ; DEST[3] = SRC[0]
>mc03    SRC, DEST       ; DEST[0] = SRC[3]

   At the risk of starting a religous "code-wars", if we assume the case
   above, (two distinct registers), we can write our VAX code as:

                                 ;                      source = S3,S2,S1,S0
      INSV    R0,#16,#8,R1       ; R1<7:0> <- R0<23:16>   dest = ??,??,??,S2
      ROTL    #-8,R1             ; rotate R1 8 right      dest = S2,??,??,??
      INSV    R0,#8,#8,R1        ; R1<7:0> <- R0<15:8>    dest = S2,??,??,S1
      ROTL    #-8,R1             ; rotate...              dest = S1,S2,??,??
      INSV    R0,#0,#8,R1        ; R1<7:0> <- R0<7:0>     dest = S1,S2,??,S0
      ROTL    #-8,R1             ; rotate...              dest = S0,S1,S2,??
      INSV    R0,#24,#8,R1       ; R1<7:0> <- R0<31:24>   dest = S0,S1,S2,S3

   7 instructions, 0 memory references....

 [ This will also work with R0 and/or R1 replaced with a memory address (as long
   as they do not overlap), but that would be hideous :-)  ]

  John Hascall
  ISU Comp Center

  p.s.  Is  ROTL #24,Rx  faster/slower than  ROTL #-8,Rx  ?  anyone?
	I'm guessing it's faster because you can write #24 as a
	short-literal...