Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!nrl-cmf!ukma!tut.cis.ohio-state.edu!bloom-beacon!mit-eddie!uw-beaver!cornell!rochester!pt.cs.cmu.edu!sei!sei.cmu.edu!firth From: firth@sei.cmu.edu (Robert Firth) Newsgroups: comp.arch Subject: Re: When is RISC not RISC? Message-ID: <8476@aw.sei.cmu.edu> Date: 8 Feb 89 14:06:24 GMT References: <4592@tekgvs.LABS.TEK.COM> Sender: netnews@sei.cmu.edu Reply-To: firth@bd.sei.cmu.edu (Robert Firth) Organization: Carnegie-Mellon University, SEI, Pgh, Pa Lines: 36 Keith Ericson writes: > Seems to me that the "reduced" is a totally incorrect moiniker (sp?): the > truly salient point is that all the instructions are equal length, to reduce > problems maintaining the instruction pipeline. In article jk3k+@andrew.cmu.edu (Joe Keane) writes: >As much as i dislike VAX instruction encoding, i can't agree with this. >Single-size instructions are nice, but you'll pay a price in code density. The >RT has two instruction sizes, and i think it was the right choice. This issue has been argued quite vigorously in the DoD RISC program, and I'd like to offer an unobjective opinion. It seems pretty clear that instruction density can be improved by having more than one length. The GE design used two lengths (16 and 32) and claimed a 15% improvement in instruction density as a result. This seems reasonable to me. However, set against that the following . more complicated instruction decode . more complicated pipeline management , more complicated Icache design . loss of one bit in span of relative branch or call If the goal is pure speed, the question I ask is: are you better off with 15% more bytes of instructions and a bigger Icache? If you can raise the hit rate from 93% to 94% you have offset the difference in instruction size (you fetch 6% rather than 7% for a reduction of 14% in instructions fetched). Moreover, very little new logic is involved, just more of the same. My view (for what it's worth) is that with CURRENT technology it is better to have all instructions the same length. However, you do need a big Icache (as I think the evolution of the Mips Inc machines demonstrates).