Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!husc6!yale!mfci!rodman From: rodman@mfci.UUCP (Paul Rodman) Newsgroups: comp.arch Subject: Re: When is RISC not RISC? Message-ID: <638@m3.mfci.UUCP> Date: 8 Feb 89 16:22:24 GMT References: <4592@tekgvs.LABS.TEK.COM> Sender: rodman@mfci.UUCP Reply-To: rodman@mfci.UUCP (Paul Rodman) Organization: Multiflow Computer Inc., Branford Ct. 06405 Lines: 58 In article jk3k+@andrew.cmu.edu (Joe Keane) writes: >Keith Ericson writes: >> Seems to me that the "reduced" is a totally incorrect moiniker (sp?): the >> truly salient point is that all the instructions are equal length, to reduce >> problems maintaining the instruction pipeline. > >As much as i dislike VAX instruction encoding, i can't agree with this. >Single-size instructions are nice, but you'll pay a price in code density. The >RT has two instruction sizes, and i think it was the right choice. Well, maybe it was the right choice. Code density is one of the LEAST important aspects of instruction set design if performance is one of your goals. When I was a grad student at CMU in 1978 we actually studied several existing architectures with an ISP simulator. One of the metrics used to "rate" the architectures was the static code size. A better one was the "dynamic" code size which would correspond to instruction cache fetches. None of these metrics really tried to quantify the things that make pipelining an instruction set difficult. Trading static code size for speed in execution is a tradeoff that most folks would love. Who cares what the size of the text is when the data is 100 Mb, anyway? The important thing is getting control bits to the functional units. Some machines try to get the best of both worlds. The Multiflow Trace, for example, uses a very long instruction word to potentially execute many operations per cycle. However, we don't want to drag around 1024 bits for EVERY instruction word , or static code size would be a problem. So we have a "mask" word in memory with the instruction "packets" that tells us which packets were unused and these packets are loaded to a zero (nop) at cmiss time. By processing the mask word at cmiss time we take something that would normally be a first order effect (i.e. cycle time) and move it to second order (cmiss time). You could even do tricks like this at page fault time (3rd order). I belive a company called Computer Consoles built a vax clone that translated the instructions at cmiss time. Personally, I think the vax has about the worst possible archtecture one could come up with (assuming you aren't PURPOSEFULLY trying to create a bad machine :-). It was great in the days when control store proms were 50ns and main memory was 1us. Today, cache rams are the same speed as the control store rams (and the control store better be rams because the microcode is so complex that you have to be able to fix it). Byte aligned instructions make the hardware more difficult and buy you nothing. So many instructions that serve no purpose, etc, etc. Blech, what a mess. And so many minds worked *hard* to create it! Ha! Paul Rodman rodman@mfci.uucp Who says engineering is a science? Engineering is an Art, and don't ever forget it!