Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!rochester!pt.cs.cmu.edu!andrew.cmu.edu!jk3k+ From: jk3k+@andrew.cmu.edu (Joe Keane) Newsgroups: comp.arch Subject: Re: When is RISC not RISC? Message-ID: Date: 9 Feb 89 01:06:14 GMT References: <4592@tekgvs.LABS.TEK.COM> , <1989Feb7.222113.7622@gpu.utcs.toronto.edu> Organization: Mathematics, Carnegie Mellon, Pittsburgh, PA Lines: 20 In-Reply-To: <1989Feb7.222113.7622@gpu.utcs.toronto.edu> Dennis Ferguson writes: > Except that, because they had to encode both the OP code and a couple of > registers into 16 bit instructions, the RT ended up with only 16 registers. > There just isn't enough room for more registers if you have to accomodate the > entire instruction set in 16 bits. I agree register sets are limited by instruction coding, but i don't think that different-sized instructions is part of the problem. Most of the RT's 32-bit instructions consist of an 8-bit opcode, two 4-bit register specifiers, and a 16-bit immediate field. You can't add more registers even if you ignore 16-bit instructions. The PDP-11 has single-size instructions (plus immediate words, does this count?) but only 3-bit register specifiers. Can't fix this either. The R2000 has big single-size instructions, but still only a 5-bit register specifier. 32 registers is nothing to get excited about. What can we do about this? More on this later...