Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bbn!husc6!m2c!wpi!jhallen
From: jhallen@wpi.wpi.edu (Joseph H Allen)
Newsgroups: comp.arch
Subject: Not-so RISCy
Keywords: risc
Message-ID: <732@wpi.WPI.EDU>
Date: 9 Feb 89 18:50:49 GMT
Organization: Worcester Polytechnic Institute, Worcester, Mass.
Lines: 14


Reduction of instruction set size/complexity is the main area of design which
enhances speed in RISC processors.  Another area which I'm wondering about is
data size handling.  Modern RISC processors handle 8, 16, 32 and 64 bit words.
Some even handle data which crosses "word" bounderies (and on some (well one)
the byte order can be changed).  The logic that must be dedicated to this must
be incedible, plus this logic is in the memory data path and therefore might a
speed constaint (especially if the data goes through the ALU before being
presented to the registers).  Would it be a terrible hardship to only have two
data sizes (perhaps character and word) and not allow words to cross word
boundaries?  Certainly it would require that people don't use "bad"
programming techniques similer to what has to be done on 68000 or IBM 360. 
But would not the improvement in speed (by freeing up chip space to allow for
more registers or to simply reduce data path delay time) be worth it?