Path: utzoo!utgpu!utstat!jarvis.csri.toronto.edu!mailrus!sharkey!atanasoff!hascall
From: hascall@atanasoff.cs.iastate.edu (John Hascall)
Newsgroups: comp.arch
Subject: RISC & context switches
Message-ID: <784@atanasoff.cs.iastate.edu>
Date: 10 Feb 89 15:25:53 GMT
Reply-To: hascall@atanasoff.cs.iastate.edu (John Hascall)
Organization: Iowa State U. Computer Science Department, Ames, IA
Lines: 54


  One of the benifits of a simple instruction set (RISC) is that it
  frees up chip area for more registers.  I think some papers have
  proposed register counts > 100, what is the largest number of
  general purpose registers in an existing chip?

  What I am curious about is, what (if any) special techniques can
  be employed to prevent a large performance hit at context switch
  time (i.e., saving all those registers for the current process,
  and restoring them for the new process)?

  Do they just rely on the PCBs being in the (data) cache?

  What about a special cache for PCBs?  Is it worth it?  Is it
  workable?

  I seem to recall there was (is?) a TI processor which had all of
  its registers in memory except 1 register which pointed to
  the other registers, so a context switch was just save/restore
  that one register.  Could a similar concept be implemented
  with all the registers in the chip?

  Consider a machine with say 32 GP registers, suppose further that
  the processor was built with say 544 (32 + (32*16)) GP registers and
  a special PID (process index) register.  Process slots 0-15 are
  reserved for "real-time" processes (when a new process is
  created, it will not use one of those slots unless it requests
  it).  Now, at context switch time if the "outgoing" process has
  an index of 0-15 no save is needed, and if the "incoming" process
  has an index also in the range of 0-15 no restore is needed either.
  For a process whose index is 16+ the 17th register set is used,
  and is saved/restored as in a "normal" system.

  It seems to me that such a scheme would take little extra hardware
  (other than the extra registers).  I just pulled the number 16 out
  of the air, any power of 2 would be as easily implemented--perhaps
  enough that on a workstation most or all of the processes could
  have a "real-time" slot.


                 PID register           program specified register number
      +-+-+-+-+-+-+-+   +-+-+-+-+-+     +-+-+-+-+-+
      | | | | | | |  ...  | | | | |     | | | | | |
      +-+-+-+-+-+-+-+   +-+-+-+-+-+     +-+-+-+-+-+
       | | | | | | | ... | | | | |       | | | | |
       \ or together to  / \ concatenate to form /
        \ form "use#17" /   \ actual register # /
	 \ signal      /     \ (if ~use#17)    /


A hair-brained scheme or what?

  John Hascall
  ISU Comp Center