Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!leah!rpi!rpics!kyriazis
From: kyriazis@rpics (George Kyriazis)
Newsgroups: comp.arch
Subject: Re: RISC & context switches
Message-ID: <571@rpi.edu>
Date: 11 Feb 89 22:04:19 GMT
References: <784@atanasoff.cs.iastate.edu> <7239@june.cs.washington.edu>
Sender: usenet@rpi.edu
Reply-To: kyriazis@turing.cs.rpi.edu (George Kyriazis)
Organization: RPI CS Dept.
Lines: 32

In article <7239@june.cs.washington.edu> robertb@uw-june.UUCP (Robert Bedichek) writes:
>In article <784@atanasoff.cs.iastate.edu> 
>             hascall@atanasoff.cs.iastate.edu (John Hascall) writes:
>> <some lines deleted>
>>
>>  I seem to recall there was (is?) a TI processor which had all of
>>  its registers in memory except 1 register which pointed to
>>  the other registers, so a context switch was just save/restore
>>  that one register...
>
>I believe that you are thinking of the TI9900, one of the first 
>16-bit microprocessors.  It was very slow, I think at least partly
>because it kept its registers in memory.
>

No, it wasn't snow because of that.  It wasn't optimised at all.
It had 4 non-overlapping clocks, and the internal algorithms were
terribly slow.  If you are thinking of the TI99/4A, yes it was much
slower simply because it was expanding each bus cycle into 6 (!!).
An 8/16 bit succesor of the 9900 the 9995, was faster than the 8088,
and the 99000 (built to fight the 68000), was benchmarking better that
the 68000 (at least that's what they claim).  

I really liked that architecture, but I guess that it wasn't enough :-)
Oh well..



  George Kyriazis
  kyriazis@turing.cs.rpi.edu
  kyriazis@rdrc.rpi.edu
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