Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: RISC & context switches
Message-ID: <1989Feb12.002935.21396@utzoo.uucp>
Organization: U of Toronto Zoology
References: <784@atanasoff.cs.iastate.edu>
Date: Sun, 12 Feb 89 00:29:35 GMT

In article <784@atanasoff.cs.iastate.edu> hascall@atanasoff.cs.iastate.edu (John Hascall) writes:
>  I seem to recall there was (is?) a TI processor which had all of
>  its registers in memory except 1 register which pointed to
>  the other registers, so a context switch was just save/restore
>  that one register.  Could a similar concept be implemented
>  with all the registers in the chip?

You can use the AMD 29000 that way, in fact, although doing register
windows is more popular in Unix environments.  If you dedicate a set of
16 registers to each process, and dedicate most of the global registers
saving the rest of the state for the processes, you can have 8 processes
running with a context-switch time of something like 17 cycles.
-- 
The Earth is our mother;       |     Henry Spencer at U of Toronto Zoology
our nine months are up.        | uunet!attcan!utzoo!henry henry@zoo.toronto.edu