Path: utzoo!utgpu!utstat!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!agate!eos!ames!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: quest for breakthroughs (long)
Keywords: architecture, breakthrough, technology
Message-ID: <21786@ames.arc.nasa.gov>
Date: 13 Feb 89 23:34:36 GMT
References: <740@tetons.UUCP>
Organization: NASA - Ames Research Center
Lines: 61

In article <740@tetons.UUCP> bb@tetons.UUCP (Bob Blau) writes:
>  Imagine that you are the enlightened head of Imaginary Computer Corp's

I need a cheaper/smaller multiport memory interface technology.

>  What are your assumptions?

>End Product: 

Workstation, Mini

>Architecture:RISC, CISC, Vector
>             multiprocessor, ...

All of the above: A fixed instruction format 64 bit supermicro for workstations
with multiple processors.

>Application: 

Engineering, Scientific

>Timeframe:   

Next year

>  What problems are you trying to solve?
>- Performance, Cost, Complexity, Size, Reliability, ...

Yes.

>- Fiberoptic advances creating 1 Gigabyte/sec cable or bus bandwidths
>  Chip pinout: 250 pins -> 400 -> 800 -> 1000 -> 2000 -> ?
>  Cable bandwidth: 100 Mbits/sec -> 500M -> 1G -> 10G -> 100G -> ?

I want to build a supermicro that is architecturally similar to a big
vector/parallel machine - so, in order to do that, I need a technology
that will lower the complexity/cost/size of a multi-port memory interface
to around $1K.  For example, suppose you had a bus-like box with 8 processor
ports and 8 Memory Bank ports.  You could plug 4 CPU's in, with 2 IO
Controllers, a Video Controller, and a spare, and each processor be able
to get full memory bandwidth barring bank conflicts.
Clock cycle time: should support clock cycle times of 20 ns.
Bus width: 64 data bits + 14 bits ECC minimum.  Up to 512 data bits wide could
potentially be useful on a more expensive model (I am not sure how you would
do the bus connections, but the bandwidth is useful.)
Total memory bandwidth: 3-25GBytes/sec total, depending on width (64-512 bits)
(I know this sounds expensive  - that is why a breakthrough is needed.)
In other words, something like a Cray Y-MP multiport memory
interface, slowed down a little bit and packaged very inexpensively and
compactly, is what is desired.






-- 
  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117