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From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: [HS]W interlocks (was: Fujitsu SPARC Interlocks)
Message-ID: <14619@cup.portal.com>
Date: 13 Feb 89 02:59:46 GMT
References: <28200269@mcdurb> <28200273@mcdurb> <3007@ardent.UUCP>
Organization: The Portal System (TM)
Lines: 15

The MIPS processors (R2000 and R3000) are the only commercial uPs I'm aware
of that are not fully interlocked; are there others?  (Not counting delayed
branches, of course, which everyone does.)

The MIPS architecture definition has one load delay slot.  Processors that
have longer load latency will simply require interlocks.  John Hennessy
contends that it will never make sense to build a processor with no load
delay slot.  As I understand it, his argument is that even with on-chip cache,
the register file will be faster to access than the cache, and if there is no
delay slot, then the machine isn't running as fast as it could and would be
better off with a faster clock and a load delay slot.

Anyone disagree?  Will there be pipelined uPs that have no delay slot?

Michael Slater    mslater@cup.portal.com