Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!agate!pasteur!ames!amdcad!weitek!mahar
From: mahar@weitek.UUCP (Mike Mahar)
Newsgroups: comp.arch
Subject: Re: [HS]W interlocks (was: Fujitsu SPARC Interlocks)
Message-ID: <410@attila.weitek.UUCP>
Date: 14 Feb 89 18:20:45 GMT
References: <28200269@mcdurb> <28200273@mcdurb> <3007@ardent.UUCP> <14619@cup.portal.com>
Reply-To: mahar@attila.UUCP (Mike Mahar)
Organization: WEITEK Corporation, Sunnyvale, CA
Lines: 14

In article <14619@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes:
>The MIPS processors (R2000 and R3000) are the only commercial uPs I'm aware
>of that are not fully interlocked; are there others?  (Not counting delayed
>branches, of course, which everyone does.)
>
The Weitek XL processor doesn't have any interlocks.  There is no delay slot
on loads for this machine.  The Multiply and Divide instructions take 6 and 16
cycles respectivly but there is still no interlock.  The floating point 
instructions take 2 or three cycles and may be pipelined.

			Mike Mahar
-- 
"The bug is in the package somewhere". |	Mike Mahar
 - Anyone who has used Ada	       | UUCP: {turtlevax, cae780}!weitek!mahar