Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: [HS]W interlocks (was: Fujitsu
Message-ID: <28200274@mcdurb>
Date: 14 Feb 89 16:02:00 GMT
References: <14619@cup.portal.com>
Lines: 17
Nf-ID: #R:cup.portal.com:14619:mcdurb:28200274:000:754
Nf-From: mcdurb.Urbana.Gould.COM!aglew    Feb 14 10:02:00 1989


>The MIPS processors (R2000 and R3000) are the only commercial uPs I'm aware
>of that are not fully interlocked; are there others?  (Not counting delayed
>branches, of course, which everyone does.)

I have been told (by a MIPSco guy making a presentation) that the second
generation MIPS processor does in fact have some interlocks, in areas
where the new implementation had longer latencies than the old.
For example, the delay slot should, in fact, be 2 instructions,
but they interlock at 1.

I'm sure that somebody from MIPS will correct me.

My point is: the question is no longer whether your machine is entirely
hardware interlocked, or entirely software interlocked;
it is, what combination of hardware and software interlocks
gets the job done.