Xref: utzoo comp.os.os9:372 comp.sys.m6809:1001
Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ukma!rutgers!att!ihlpl!knudsen
From: knudsen@ihlpl.ATT.COM (Knudsen)
Newsgroups: comp.os.os9,comp.sys.m6809
Subject: Re: timing fix
Summary: Really need a separate NOR gate?
Message-ID: <8907@ihlpl.ATT.COM>
Date: 8 Feb 89 18:13:47 GMT
References: <8902080504.AA07308@decwrl.dec.com>
Organization: AT&T Bell Laboratories - Naperville, Illinois
Lines: 21

In article <8902080504.AA07308@decwrl.dec.com>, burke_vern@dneast.dec.com (Mah biscuits 're burnin'!-Yosemite Sam,_Roger Rabbit_) writes:

> 	I added a NOR gate to my coco III to duplicate the original coco's
> 	gating for the 74ls138.My performance peripherals dual mode

Thanks for posting this.  I'd been wondering about this timing nit
ever since I got the Tech Manual for my Coco 3.
I've been afraid to tinker with it, thinking that the extra gating
might mess something else up.  You have proven it won't.

Question:  Do you really need a separate NOR gate?  The '138
has three enables -- one positive, two negative -- that are internally
ANDed.  One of these is used for the pulse itself.  Now if one
of the negative enables is left over, shouldn't you be able to lift
its hard-wired ground and feed the enabling clock into it?

I'll have to check the schematic tonite.  Meanwhile, could you post
more details?  Thanks, mike k
-- 
Mike Knudsen  Bell Labs(AT&T)   att!ihlpl!knudsen
"Five hundred twelve K bytes of RAM ... out of control ... "