Path: utzoo!utgpu!utstat!jarvis.csri.toronto.edu!mailrus!ncar!tank!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: When is RISC not RISC?
Message-ID: <28200275@mcdurb>
Date: 15 Feb 89 16:45:00 GMT
References: <747@atanasoff.cs.iastate.edu>
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Nf-ID: #R:atanasoff.cs.iastate.edu:747:mcdurb:28200275:000:470
Nf-From: mcdurb.Urbana.Gould.COM!aglew    Feb 15 10:45:00 1989


>Why not have a *real* pipelined memory system and a compiler than can
>handle more than one miserable outstanding load in flight? Or have both.
>
>
>    Paul Rodman

Denelcore's HEP.

We discussed barrell processors (processors that execute a different
process at every pipe stage, hence no dependencies) a while back;
someone (I think it was John Mashey) posted a rather good argument
against them. Does anyone have that around? (BTW, is comp.arch
archived anywhere?)