Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!ico!rcd
From: rcd@ico.ISC.COM (Dick Dunn)
Newsgroups: comp.arch
Subject: Re: When is RISC not RISC?
Summary: courtesy, please?
Message-ID: <15053@ico.ISC.COM>
Date: 17 Feb 89 05:28:35 GMT
References: <747@atanasoff.cs.iastate.edu> <28200275@mcdurb> <649@m3.mfci.UUCP>
Organization: Interactive Systems Corp, Boulder, CO
Lines: 27

In article <649@m3.mfci.UUCP>, rodman@mfci.UUCP (Paul Rodman) writes:
...
> >Denelcore's HEP.
...
> Yuk. Please don't bring up that pile of junk. 

This is rude, out of place in the newsgroup, and unfounded anyway.  The
ideas that Denelcor (mostly Burton Smith) attempted to develop in the HEP
were reasonably well-founded; pieces of them can be found in more contem-
porary designs.  Remember that the HEP design was really mid-'70's, and
also keep in mind that corporate vicissitudes (financing, contracts, and
all that piddly money stuff) do not determine technical merit.

> I was referring more to our machine...

How nice.  Slam machine X, then boost your own.

> ...In some 
> cases a data cache is useful for reducing latency if the hit rate will be
> high enough. Of course, your compiler must do a good job
> about deciding when to go for the cache...

Remarkable as it may seem, there are data caches with very high hit rates,
and the compilers don't even have to worry about their existence.
-- 
Dick Dunn      UUCP: {ncar,nbires}!ico!rcd           (303)449-2870
   ...Just say no to mindless dogma.