Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!sun!pitstop!sundc!seismo!uunet!microsoft!w-colinp
From: w-colinp@microsoft.UUCP (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: quest for breakthroughs (long)
Message-ID: <679@microsoft.UUCP>
Date: 17 Feb 89 14:07:00 GMT
References: <740@tetons.UUCP> <3780@tekig5.PEN.TEK.COM> <11780@haddock.ima.isc.com>
Reply-To: w-colinp@microsoft.uucp (Colin Plumb)
Organization: very little
Lines: 15

suitti@haddock.ima.isc.com (Stephen Uitti) wrote:
> Don't invent a new memory store type.  Just put a few pages of
> physical RAM on the chip.  This was done for some 8 bit controller
> type chips way back when (for different reasons).

Also, on the Inmos Transputer.  4K of on-chip memory in the T800,
16K on the T810.  On the T810, it's 64 bits wide, too.

I'd still rather have cache.  It's a pain to allocate that space
unless you take over the whole processor with your application
and do it at compile-time.
-- 
	-Colin (uunet!microsoft!w-colinp)

"Don't listen to me.  I never do."