Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!uxc!uxc.cso.uiuc.edu!m.cs.uiuc.edu!robison From: robison@m.cs.uiuc.edu Newsgroups: comp.arch Subject: Scoop on Intel N-10? Message-ID: <3300053@m.cs.uiuc.edu> Date: 16 Feb 89 23:12:00 GMT Lines: 16 Nf-ID: #N:m.cs.uiuc.edu:3300053:000:608 Nf-From: m.cs.uiuc.edu!robison Feb 16 17:12:00 1989 There was a blurb on Intel's N-10 processor in the Chicago Tribune today. It was announced at the Int. Solid State Circuits Conference. The only technical info in the Tribune is that the N-10 is a 64-bit processor with a five times bigger than usual chip size, and does 150 MIPS. (Whatever that means!) What's the N-10's architecture? Floating point? Vector? MIMD? Just really fast transistors? Enquiring minds want to know. Arch D. Robison University of Illinois at Urbana-Champaign CSNET: robison@UIUC.CSNET UUCP: {pur-ee,convex}!uiucdcs!robison ARPA: robison@CS.UIUC.EDU (robison@UIUC.ARPA)