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From: khb%chiba@Sun.COM (chiba)
Newsgroups: comp.arch
Subject: Re: RISC & context switches
Message-ID: <90338@sun.uucp>
Date: 18 Feb 89 00:38:07 GMT
References: <89Feb12.125852est.10867@ephemeral.ai.toronto.edu> <103@eve.oz>
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Reply-To: khb@sun.UUCP (chiba)
Organization: Sun Microsystems, Mountain View
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In article <103@eve.oz> andrew@eve.oz (Andrew McRae) writes:
>From article <89Feb12.125852est.10867@ephemeral.ai.toronto.edu>, by bradb@ai.toronto.edu (Brad Brown):
>>> [ Discussion about multiple register sets ]
>> 
.....
>The Concurrent Computer Corp. 3200 series has multiple register
>sets (up to 16), the operative set selected by a 4 bit field in the
>processor status register. Generally these are not used to speed
...
>tied up with the architecture (e.g. at interrupt time some of
>the registers had useful values stored in them by the microcode
>such as vector number, device address, previous status/program
>counter etc). Not being a stack based machine, the register
>swapping tended to be fundamental to the way the OS did things (I'm
>speaking of course for the native OS/32, not Unix).
>
>I'm suprised that this idea (different register sets for different
>interrupt levels) has not been taken up in some of the more modern
>architectures, but there are problems (try doing a splX, and see
>if your registers hold the same values...). 

The IBM Series/1 also had this sort of set up (4 sets, as best I can
recall). 

More modern architectures haven't done this because most folks aren't
trying to optimize that kind of context switch (at least none of the
popular benchmarks are testing for it). It _is_ handy for certain
types of real time tasking...so perhaps folks deeply involved in that
area can comment.

Wearing my application programmer hat, I'd rather have all those
registers for _my_ task, if they can be usefully employed. 
Keith H. Bierman
It's Not My Fault ---- I Voted for Bill & Opus