Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: When is RISC not RISC?
Message-ID: <28200277@mcdurb>
Date: 17 Feb 89 23:37:00 GMT
References: <747@atanasoff.cs.iastate.edu>
Lines: 10
Nf-ID: #R:atanasoff.cs.iastate.edu:747:mcdurb:28200277:000:312
Nf-From: mcdurb.Urbana.Gould.COM!aglew    Feb 17 17:37:00 1989


>The architecture is broken if I can't at least do 1 load/store 
>(from memory,please) per flop. :-)  
>
>    Paul Rodman
>    rodman@mfci.uucp

Actually, given some of the instruction frequency statistics
I've been seeing recently, you need about 3 load/stores
per arithmetic operation. From cache, admittedly.