Path: utzoo!attcan!uunet!mcvax!ukc!warwick!inmos!des
From: des@inmos.co.uk (David Shepherd)
Newsgroups: comp.arch
Subject: Re: RISC & context switches
Message-ID: <827@brwa.inmos.co.uk>
Date: 17 Feb 89 18:19:20 GMT
References: <784@atanasoff.cs.iastate.edu> <640@m3.mfci.UUCP>
Reply-To: des@inmos.co.uk (David Shepherd)
Organization: INMOS Limited, Bristol, UK.
Lines: 28

In article <640@m3.mfci.UUCP> colwell@mfci.UUCP (Robert Colwell) writes:
>In article <784@atanasoff.cs.iastate.edu> hascall@atanasoff.cs.iastate.edu (John Hascall) writes:
>>  I seem to recall there was (is?) a TI processor which had all of
>>  its registers in memory except 1 register which pointed to
>>  the other registers, so a context switch was just save/restore
>>  that one register.  Could a similar concept be implemented
>>  with all the registers in the chip?
>
>I think this was the TI 9900, the first 16-bit micro,

The INMOS transputer has a similar idea. It has a 3 deep register stack, an
instruction pointer and a workspace pointer that points into memory and 
(currently) 4k of on chip RAM. Loading and storing to on chip RAM relative to
the workspace gives you 16 fast (1 cycle store, 2 cycle load) "registers" and
256 slightly slower (2 cycle store, 3 cycle load) "registers". Switching from
one concurrent process to another only involves storing the instruction pointer,
workspace pointer, adding the descheduled process to the end of the scheduling
queue and taking the new one off the front.

>							which for some reason
>didn't seem to catch on very well. 

hmmm ... perhaps it didn't have a decent C compiler either ;-)

david shepherd
INMOS ltd

disclaimer: any opinions expressed above are mine -- so don't steal them