Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!amdahl!nsc!taux01!yuval From: yuval@taux01.UUCP (Gideon Yuval) Newsgroups: comp.arch Subject: Re: Endian reversing MOVEs Message-ID: <1089@taux01.UUCP> Date: 19 Feb 89 09:20:23 GMT References: <759@atanasoff.cs.iastate.edu> <772@atanasoff.cs.iastate.edu> Reply-To: yuval@taux01.UUCP (Gideon Yuval) Organization: National Semiconductor (IC) Ltd, Israel Lines: 23 If you need wrong-endian language-semantics on right-endian H/W, the fastest way out is as follows: Define a new architecture, in which a byte's logical address is the NEGATION of its physical address (one's complement works better, but that's a 2nd-order effect). the old load/store op-codes become, under this new architecture, load&swap and store&swap op-codes; and if we restrict compiled code to a RISC-style load/store/reg-op architecture, the ONLY op-codes that know about byte-sex are load/store: registers have no high/ low addressing inside them, and memory data have no LSB/MSB in them!. This new architecture (which is simply another way to look at the existing H/W!) lets wrong-endian code get compiled for a right-endian CPU. The main penalty is in pointer-management: to dereference a pointer, we have to negate (or: one's complement) it first; and the same pointer cannot be used for byte, word and Dword access; but the compiler gurus estimate the time-penalty at 10-30% ("C" code), less for Fortran, and as near 0.0% for Cobol as makes no difference. -- Gideon Yuval, yuval@taux01.nsc.com, +972-2-690992 (home) ,-52-522255(work) Paper-mail: National Semiconductor, 6 Maskit St., Herzliyah, Israel TWX: 33691, fax: +972-52-558322