Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!bu-cs!purdue!decwrl!sun!pitstop!sundc!seismo!uunet!portal!cup.portal.com!mslater From: mslater@cup.portal.com (Michael Z Slater) Newsgroups: comp.arch Subject: Re: N-10 query Message-ID: <14860@cup.portal.com> Date: 20 Feb 89 00:31:02 GMT References: <25321@cornell.UUCP> Organization: The Portal System (TM) Lines: 69 There have been several requests for N10 info, and since no one from Intel seems to be ready and willing to reply, I'll give it a shot. First, while Intel did give a paper on a "64-bit" microprocessor at ISSCC, they did not give it the name N10, and it was not in any way a product announcement. That said, I think it is the same thing as what has been called the N10, and Intel has scheduled a press conference for Feb 27 at which they are expected to formally unveil the new chip. (The press announcement, by the way, included a pair of socks, with a wrapper that says "On February 27, Intel will knock your socks off".) The March issue of Microprocessor Report will have an in-depth report on the N10, but for now, here are a few details based on the information presented at ISSCC. Intel calls the chip a "64-bit" processor, but this is questionable. It does have a 64-bit data/instruction bus, but instructions are 32 bits each, the integer registers are 32 bits each, and the ALU is 32 bits wide. In favor of the 64-bit argument, the FP registers can be accessed as 64 bits wide, and there are three 64-bit buses in the FP section. The chip has two main computational sections: an integer unit and a floating-point unit. The FP unit has a separate adder and multiplier, and they can both run concurrently. The FP and integer can also run at the same time, so a total of 3 operations can be started in the same clock cycle. The chip has a mode in which one integer and one FP instruction are read from the instruction cache in each clock cycle. There is also a "graphics unit" which uses the FP data paths. It's not clear yet just what this does, but Intel says it provides 10 x the performance of the integer unit for things like shaded triangles. The chip includes a 4K instruction cache and an 8K data cache. Both are 2 way set associative. The data cache is write-back, and there is no snooping, so shared data cannot be cached. The MMU is 386-compatible, but without segmentation. At ISSCC, Intel quoted figures of 105,000 Dhrystones and 21 double precision Linpack MFLOPS at 50 MHz. Two caveats here -- quoting 50 MHz numbers at ISSCC doesn't mean that commercial parts will run at 50 MHz anytime soon, and the MFLOPS number likely is for hand-optimized code, not compiler generated. Graphics performance was stated as 60K Gouraud shaded triangles per second. It seems likely that this chip will displace MIPS for the title of world's fastest microprocessor, at least for a while. I'm told samples are already out, and production shouldn't be too far behind. For systems designed for 3D graphics, it seems that the N10 will provide a level of performance way beyond that attainable with any other single-chip processor solution. (It isn't as fast as something like SGI's geometry engine, but that is a much more expensive multi-chip solution.) If this chip had been announced a year ago, it might have been a major competitor of SPARC, MIPS, and the 88K for the gneral UNIX workstation market. I think it is now too late, however, for it to compete for the mainstream Unix boxes. Software developers don't want yet another architecture to port to. But for graphics workstations, it may be a big hit. It will also be popular for graphics accelerators, either as add-in boards or as a coprocessor in new system designs. More details as they become public. Michael Slater, Editor and Publisher, Microprocessor Report 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677 fax: 415/494-3718 email: mslater@cup.portal.com