Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!sm.unisys.com!ucla-cs!marc
From: marc@oahu.cs.ucla.edu (Marc Tremblay)
Newsgroups: comp.arch
Subject: Re: Bus History Units
Message-ID: <20846@shemp.CS.UCLA.EDU>
Date: 22 Feb 89 04:01:43 GMT
References: <4316@pt.cs.cmu.edu> <28200280@mcdurb>
Sender: news@CS.UCLA.EDU
Reply-To: marc@cs.ucla.edu (Marc Tremblay)
Organization: UCLA Computer Science Department
Lines: 26

In article <28200280@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:
>Well, from the academic side Berkeley's HPSm project _built_ a 
>microprocessor with Tomasulo scheduling, and backup by copying
>of the register file.

Did they actually fabricate it? 

>    Myself, I'm flogging a hardware renaming technique that is
>considerably less expensive than backing up the entire register
>file.

We have designed a mechanism that "rolls back" the register file
without much area penalty. The register file is not replicated,
instead the "writes" into the register file are delayed for a 
few cycles until there is no more need to retrieve them. 
The register address of the writes is also stored in 
the "delayed-write buffer" allowing subsequent "reads" 
to access the up-to-date value of a register.
You can imagine the mechanism as "forwarding" for multiple registers.
The delayed-write buffer can be invalidated partially of completely
in a single cycle.
If more information is needed I can post or e-mail the references.

					Marc Tremblay
					marc@CS.UCLA.EDU
					Computer Science Department, UCLA