Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!poe.ufnet.ufl.edu!seeger
From: seeger@poe.ufnet.ufl.edu (F. L. Charles Seeger III)
Newsgroups: comp.arch
Subject: Re: Don't look back...
Message-ID: <19814@uflorida.cis.ufl.EDU>
Date: 22 Feb 89 15:48:17 GMT
References: <747@atanasoff.cs.iastate.edu> <28200275@mcdurb> <4290@pt.cs.cmu.edu> <13582@winchester.mips.COM> <4330@pt.cs.cmu.edu>
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Reply-To: seeger@iec.ufl.edu (F. L. Charles Seeger III)
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In article <4330@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
|The breakthrough I'd like to see, is chip vias. For the hardware-
|impaired, what I mean is, I'd like to see signal paths between the two
|surfaces of a chip. I'd like to take a stack of naked chips, and then
|solder them together into a solid cube.

I believe through-wafer vias are being done, at least in some labs.  However,
as you might expect, they are rather large by VLSI standards.  Memory-check:
my recollection could be about a proposal to do these vias, rather than a
report of it being done.

AT&T is working on using wafers as circuit boards, with >= 4 conducting
layers, including power and ground planes.  Individual chips are mounted
to the wafer with solder techniques similar to SMT.  A big win here is that
this mounting is done before packaging, so that the IO pads on the chips
can be scattered about the chip anywhere that is most convenient (i.e. the
pads need not be around the periphery).  The initiative for this work was
to increase the interconnect density, which hasn't been keeping pace with
chip density.  You can then mount your CPU, MMU, FPU, sRAM, dRAM, etc. all
on one wafer, while still using different fabs for the different chips.
Though their work is currently planar, it seems that combining this
technology with through-wafer vias would point in the direction that you
suggest.

--
  Charles Seeger            216 Larsen Hall		+1 904 392 8935
  Electrical Engineering    University of Florida
  seeger@iec.ufl.edu        Gainesville, FL 32611