Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!mit-eddie!uw-beaver!blake!ogccse!littlei!omepd!psu-cs!reed!tektronix!tekecs!frip!andrew
From: andrew@frip.wv.tek.com (Andrew Klossner)
Newsgroups: comp.arch
Subject: Re: [HS]W interlocks
Message-ID: <11058@tekecs.GWD.TEK.COM>
Date: 21 Feb 89 21:57:17 GMT
References: <28200269@mcdurb> <28200273@mcdurb> <3007@ardent.UUCP> <14619@cup.portal.com> <24435@amdcad.AMD.COM>
Sender: andrew@tekecs.GWD.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 16

[]

	"If an on-chip I-cache can be built that will supply an
	instruction in a single-cycle (which it *has* to, in order to
	run at 1 inst/cycle), why can't a D-cache with the same
	characteristics exist?"

The I-cache has a strong hint as to which instruction will next be
fetched, and can have it ready.  The D-cache has no such hint.

And, on many machines, even the I-cache will take an extra cycle to
supply an instruction if you surprise it by taking an unexpected branch
(or by not taking an expected branch).

  -=- Andrew Klossner   (uunet!tektronix!orca!frip!andrew)      [UUCP]
                        (andrew%frip.wv.tek.com@relay.cs.net)   [ARPA]