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From: rpw3@amdcad.AMD.COM (Rob Warnock)
Newsgroups: comp.arch
Subject: Re: Barrel processors & string ops [really: Don't look back...]
Message-ID: <24582@amdcad.AMD.COM>
Date: 23 Feb 89 13:27:31 GMT
References: <747@atanasoff.cs.iastate.edu> <28200275@mcdurb> <4290@pt.cs.cmu.edu> <13582@winchester.mips.COM>
Reply-To: rpw3@amdcad.UUCP (Rob Warnock)
Organization: [Consultant] San Mateo, CA
Lines: 48

As John Mashey says, with current chip technology, barrel processors don't
seem to make much sense. But there *are* upcoming technologies for which
barrel architectures will make sense, at least for a time, just as there was
a time in the past in which they made sense -- when memory was much slower
than the CPU logic (e.g. the CDC 6600 Peripheral Processors).

Case in point: Several groups -- most notably that I know of, Alan Huang
et. al. at Bell Labs (see some recent issue of "Scientific American" or
"Discover", I forget) -- are working on true optical computers, where the
fundamental logic operations are done with non-linear optics. The total
"state" of the CPU might be in the pattern of on/off dots in a planer wavefront
of light. A "microcycle" would consist of that wavefront travelling through
the "logic", mixing with itself and getting pieces sliced and diced, passing
through a regenerator (amplifier/limiter), and looping back to the beginning.
(This would *really* be done with mirrors!) That is, all of the optical devices
("gates", if you like) would be operating in parallel, on different pieces of
the wavefront.

Now I'm guessing these machines will initially have optical loop paths
("microcycle" times?) in the low to medium nanoseconds (circa 5ns/meter
in glass?), since they won't be sub-miniturized (initially). But from what
I hear, even initially the optical devices will be *very* fast (just a few
picoseconds or less), so that you'll only be "using" the gates for the
"thickness" of the wavefront. So they're already thinking about taking
another wavefront and positioning it "behind" the first one (of course
with some guard time to avoid interference).

Voila! A barrel processor! In the limit, a given hunk of glass/&c. could
support "loop_time/switching_time" CPUs in the barrel. And if I/O or access
to "main" memory (whatever that might be) was slow, it might make sense to
artificially increase the microcycle (loop) time to match the external world,
which at the same time lets you stack more CPUs in the barrel. (Pushing the
analogy, the width of one "stave" is fixed by the speed of the optical logic,
including guard bands. "Staves/sec", or circumferential speed is fixed by
speed-of-light in the glass/silicon/air/whatever in the loop. But the "RPMs"
can be slowed by adding staves to the circumference of the barrel.)

Anyway, just to point out that there is some chance that barrel processors
may live again someday...


Rob Warnock
Systems Architecture Consultant

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