Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!haven!uvaarpa!mcnc!ece-csc!paulf
From: paulf@ece-csc.UUCP (Paul D. Franzon)
Newsgroups: comp.arch
Subject: Re: Don't look back...
Message-ID: <3926@ece-csc.UUCP>
Date: 23 Feb 89 14:12:25 GMT
References: <747@atanasoff.cs.iastate.edu> <28200275@mcdurb> <4290@pt.cs.cmu.edu> <13582@winchester.mips.COM> <4330@pt.cs.cmu.edu> <19814@uflorida.cis.ufl.EDU>
Reply-To: paulf@ece-csc.UUCP (Paul D. Franzon)
Organization: North Carolina State University, Raleigh, NC
Lines: 31

In article <19814@uflorida.cis.ufl.EDU> seeger@iec.ufl.edu (F. L. Charles Seeger III) writes:
>In article <4330@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
>|The breakthrough I'd like to see, is chip vias. For the hardware-
>|impaired, what I mean is, I'd like to see signal paths between the two
>|surfaces of a chip. I'd like to take a stack of naked chips, and then
>|solder them together into a solid cube.
>
>I believe through-wafer vias are being done, at least in some labs.  However,
>as you might expect, they are rather large by VLSI standards. 

Hughes is working on mechanical through wafer vias.  They are large (0.5mm
square) but you can put circuits underneath them.  They have proposed
multi-layer structures.  I've heard nothing about mechanical reliability.

AT&T is working on through-wafer optical interconnects.  At the moment this
is at a research stage only.

>
>AT&T is working on using wafers as circuit boards, with >= 4 conducting
>layers, including power and ground planes.  Individual chips are mounted

This effort has been dropped.  Several other groups are working on Ceramic
or Al high density "circuit boards", on which chips are flip mounted.
This gives you a very high density I/O capability and very fast interconnect.
Some people here are currently  exploring structures that can use these
capabilities effectively.


-- 
Paul Franzon					Aussie in residence
Ph. (919) 737 7351				ECE Dept, NCSU