Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!husc6!yale!mfci!rodman
From: rodman@mfci.UUCP (Paul Rodman)
Newsgroups: comp.arch
Subject: Re: Don't look back
Message-ID: <661@m3.mfci.UUCP>
Date: 23 Feb 89 19:39:11 GMT
References: <13582@winchester.mips.COM> <20667@lll-winken.LLNL.GOV> <7330@pyr.gatech.EDU> <656@m3.mfci.UUCP> <20821@lll-winken.LLNL.GOV>
Sender: rodman@mfci.UUCP
Reply-To: rodman@mfci.UUCP (Paul Rodman)
Organization: Multiflow Computer Inc., Branford Ct. 06405
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In article <20821@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov.UUCP (Eugene Brooks) writes:
>Whether or not the Cray-3 is manufacturable, there will certainly be super-
>computers with many gigaflops of VECTOR performance in the near term.  

Please stop using the word VECTOR. use "large data aggregate" or "parallel"
instead. There are many, many problems that are not vectorizable but
have large amounts of parallelism. You would call it "scalar" parallelism, 
but you would be in error if you thought small RISC chip would compete
in performance with a VLIW (or WISC) machine.

Its interesting the same folks that find "CISC" non-optimal can 
also refer to vector architectures without flinching! I'm waiting for the
day when somebody announces a SPARC or MIPS based processor with a vector
unit! :-) :-) 

[Reminds me of chess programs that follow MCO for the opening
but as soon as their out of the "book" they have no idea why they did what
they did, and they start undoing moves!]

>We were
>talking about scalar performance, and not vector performance.  Certain codes
>which are heavily run on Cray machines are scalar and would score high hit
>rates in a rather small cache.  
>I predict that a microprocessor will outrun the
>scalar performance of the Cray-1S within a year.   The "supercomputers" will
>only hold on for those applications which are 99% vectorized, 
>which are darned
>few, and because of this supercomputers will share the computer center floor
>with micro based hardware soon, and on an equal footing.
>

Well, I have more faith in parallel compilation than you seem to. Probably
because I've been able to build hardware for some of the best compiler-writers 
in the world.

I *DO* agree that canonical supers are dead ducks, in short order. 
VLIWs using VLSI to much greater advantage will replace them. 



    Paul K. Rodman 
    rodman@mfci.uucp