Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!leah!itsgw!steinmetz!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: In defense of the VAX
Message-ID: <2349@scolex.sco.COM>
Date: 23 Feb 89 23:38:29 GMT
References: <2324@scolex.sco.COM> <9620@lanl.gov>
Reply-To: seanf@scolex.UUCP (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 41

In article <9620@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>From article <2324@scolex.sco.COM>, by seanf@sco.COM (Sean Fagan):
>> [...]                                     Not providing an instruction can
>> cause the compiler writers to throw their hands up in the air (watch me,
>> sometime, when I take a look at the 370 instruction set), while providing
>> excess instructions can (and usually do) slow the machine down.
>>
>I disagree here.  A larger instruction set actually makes compiler writing
>HARDER - not easier.

I was *not* advocating a *large* instruction set, only a useful one.  As I
continuously state, the instruction set of the CDC Cyber 170 machines is
*very* close to what I want (not completely, but darn close), and it is, by
most definitions, a RISC machine (although, again, I prefer RISCC to RISC).

Now, to advocate a large instruction set:  for the compiler, do what (I
think) gcc does.  If you're not optimizing, just spit out the instructions
in the closest form to your internal representation (gcc has a bunch of
built-in "insn"'s that it uses).  If you are optimizing, try to come up with
the more complex instructions that will do what you want.  While I will
admit that gcc is not the worlds simplest compiler, it's not terribly
complex, and fairly easy to port to both RISC and CISC.

>[comments about pipelines deleted]

Uhm, even on most "pure" RISC machines, the compiler has to worry about the
pipeline (things like delayed branches et al).  The concern is smaller, to
be sure, but it is still there.  Another approach is to do what Seymour does
on Cybers and Crays:  use scoreboarding.  That way, even if your register
selection is wrong, you won't screw things up, you will merely run a bit
slower (on *that* model of the CPU.  If a later model speeds things up, then
you may not even have that slowdown).

Note:  this is getting very close to not being comp.arch, but
comp.compilers.  It stil has some architectural subjects, so I'm not
cross-referencing it (yet).

-- 
Sean Eric Fagan  | "What the caterpillar calls the end of the world,
seanf@sco.UUCP   |  the master calls a butterfly."  -- Richard Bach
(408) 458-1422   | Any opinions expressed are my own, not my employers'.