Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Don't look back
Message-ID: <22286@ames.arc.nasa.gov>
Date: 27 Feb 89 21:51:06 GMT
References: <13582@winchester.mips.COM> <20667@lll-winken.LLNL.GOV> <7330@pyr.gatech.EDU> <656@m3.mfci.UUCP> <20821@lll-winken.LLNL.GOV> <661@m3.mfci.UUCP>
Sender: usenet@ames.arc.nasa.gov
Organization: NASA - Ames Research Center
Lines: 48

In article <661@m3.mfci.UUCP> rodman@mfci.UUCP (Paul Rodman) writes:
>In article <20821@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov.UUCP (Eugene Brooks) writes:
>>computers with many gigaflops of VECTOR performance in the near term.  
>Please stop using the word VECTOR. use "large data aggregate" or "parallel"
>instead. There are many, many problems that are not vectorizable but

It makes sense to use VECTOR when that is what you mean.  The poster was
correct - higher speed vector processors are, in a sense, a known quantity.
Given a level of technology, it is a known problem of how to build a high
performance vector processor with a known behavior relative to a scalar
processor of the same technology.  Parallel processing is not, yet,
equivalent, though the number of parallel approaches to solving problems
is increasing.

>day when somebody announces a SPARC or MIPS based processor with a vector
>unit! :-) :-) 

I have not looked at the SPARC architecture in sufficient detail to know
whether a vector processor that is upward compatible with SPARC is a good
idea, but I suspect it is.  After all, the Cray machines and the CDC Cyber 205,
without their vector capabilities, are high performance "RISC" machines
(load store, instruction set which is easily pipelined, simple addressing modes,
simple R-to-R instructions).

Anyway, a vector micro makes perfect sense if you can build a data path into
and out of it that is wide enough.  If VLIW matures, you can expect to see
some VLIW "vector" micros.  There is already at least one machine that is close
to this - the Weitek 64 bit vector micro.

>I *DO* agree that canonical supers are dead ducks, in short order. 
>VLIWs using VLSI to much greater advantage will replace them. 

I'm not sure what a "canonical super" is, but VLIW machines are still SIMD,
like vector machines (of which they are a generalization from a certain point
of view).

A "true parallel" machine would be MIMD.  Like the Cray X-MP and its successors,
which allow true parallelism, but with a relatively small number of processors.
I note that Cray, CDC/ETA, Convex, etc., all seem to have concluded that
a vector (or possibly VLIW machine in the future) processor makes a jim dandy
building block to build a parallel machine out of, but that building a purely
parallel machine with only SISD sub-processors is not optimal.


  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117