Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cwjcc!gatech!hubcap!ncrcae!ncr-sd!hp-sdd!hplabs!hpfcdc!hpldola!hp-lsd!prisma!mo
From: mo@prisma
Newsgroups: comp.arch
Subject: Re: Not-so RISCy
Message-ID: <2700008@prisma>
Date: 24 Feb 89 15:43:00 GMT
References: <732@wpi>
Lines: 43

The Acorn Risc Machine (ARM) is a very interesting beast.
All of its instructions are conditional in that they look
at the condition codes.  Further, since the machine does NOT
do delayed branches and it has a simple pipe, branches are
a bit more expensive that might be expected.  Hence, it makes 
sense in many cases to do an if-then-else as

	condition set
	true: instr
	true: instr
	true: instr
	true: instr
	true: instr
	true: instr
	false: instr
	false: instr
	false: instr
	false: instr
	false: instr
	false: instr

where the processor just falls through at noop speeds which it does
at one cycle per noop.  I don't remember exactly when the
tradeoff occurs, but it is surprisingly effect.

Further, the ARM folks took a slightly different view of RISC.
To paraphrase the conversation I had with them:

	The usual RISC folks ask the question: what's the best
	way to use 200k transistors in building a VLSI cpu.
	We (Acorn) asked: How do we build the simplest, dirt-cheapest
	cpu possible in 20K transistors that still gets good
	performance?

Well, the ARM is pretty spiffy.  It is already being used by
at least one peripheral controller company because "where else
can you get 6 mips for $35 with a decent instruction set and
large address space that already has a good C compiler and a
decent (Unix-based) development environment?"

All in all, a very tasty piece of work.  

	-Mike