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From: turner@uicsrd.csrd.uiuc.edu
Newsgroups: comp.arch
Subject: Re: Don't look back...
Message-ID: <43700051@uicsrd.csrd.uiuc.edu>
Date: 24 Feb 89 16:59:00 GMT
References: <4330@pt.cs.cmu.edu>
Lines: 32
Nf-ID: #R:pt.cs.cmu.edu:4330:uicsrd.csrd.uiuc.edu:43700051:000:1677
Nf-From: uicsrd.csrd.uiuc.edu!turner    Feb 24 10:59:00 1989


In article <4330@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
> The breakthrough I'd like to see, is chip vias. For the hardware-
> impaired, what I mean is, I'd like to see signal paths between the two
> surfaces of a chip. I'd like to take a stack of naked chips, and then
> solder them together into a solid cube.

I just heard a talk by Kai Hwang who reported that Hughes labs has
produced 4" wafers in stacks of 6 that implement an array of
processors 32x32 in size!  He only had one slide on this, and he said
he had taken it from Hughes.  The specs I can remember said that 1"
square of the wafer contained circuitry.  It was all CMOS, and at
10MHz consumed 1.3W.  I believe that the processors they are talking
about are bit sliced - but I'm not sure.  They have plans for much
larger scale (512x512 procs) on 6" wafers, sometime around '93.

Meanwhile I personally feel that this type of technology has *lots* of
obstacles to overcome.  1 - heat (obviously).  2- fault tolerance to
an unheard of degree.  Think about it, if a single wafer has a fault
in a column the system may have to eliminate the entire column to
avoid it!  3- I/O how do you think the problem of pin limitation
applies to the square/cube law?

Overall, not a pretty picture.  But *I* sure won't say it can't be done.

---------------------------------------------------------------------------
 Steve Turner (on the Si prairie  - UIUC CSRD)

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