Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!rochester!rutgers!mcnc!duke!helios!vishin
From: vishin@helios.cs.duke.edu (Sanjay Vishin)
Newsgroups: comp.lsi
Subject: "4 phase clocks"
Keywords: VLSI, clocking, dynamic logic
Message-ID: <13651@duke.cs.duke.edu>
Date: 24 Feb 89 18:59:20 GMT
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 What are the reasons which would make a designer opt for a
 4 phase clocking scheme, rather than a 2 phase(solid, safe) one ?

 Some of the reasons I can think of are 4 phase precharged PLA's
 (so if you have a lot of PLA's in your design maybe), or in a
 2/3 bus microcoded processor with pipes (to ease the design of
 the micro-cycles(?)), or a pipelined processor (RISC -2 uses 4 phase clocks),
 Processors with dynamic control logic (The Bellmac processor uses
 domino gates in its control/data (?)).


 Vishin.



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